1. Field of the Invention
This invention pertains to a digital switching system and more particularly to an apparatus for testing ATM (Asynchronous Transfer Mode) channels, according to a multistage self-routing method, to integrally switch information or payload traffics having different traffic characteristics, such as moving images, numerical data and voices, by using an ATM transmission system like a broadband integrated services digital network (B-ISDN).
2. Description of the Related Art
With the widespread use of data communications, public switched networks are now required to perform high-quality data communications, as well as the traditional voice communications.
A B-ISDN has begun to be utilized as a communications network not only for low-speed data, such as voice data, but also for high-speed data having a transfer rate between one hundred fifty megabits per second (150 Mbps) and six hundred megabits per second (600 Mbps), such as moving images, and various interfaces have begun to be standardized. The CCITT (International Telegraph and Telephone Consultative Committee) is currently working on its advisory report on the ATM transmission system, which is an essential technology for realizing a B-ISDN, to be submitted in 1992.
An ATM communications network transmits and exchanges information or payload data carried in different bands divided and housed in fixed-length data units called cells, to which headers are attached. A header contains a virtual channel identifier (VCI) for identifying the receiving side subscriber and a virtual path identifier (VPI) for identifying the path within the current ATM exchanger, in addition to other pertinent information e.g. on a payload type and a cell loss priority in case of discarding cells, as well as a CRC (cyclic redundancy checking) code for error correction. Thus, an ATM switching system uses the headers to enable hardware to transfer and switch cells to the receiving side subscriber at a high speed.
Since an ATM switching system requires cells to carry only necessary information, it can more efficiently transmit burst signals than a conventional STM (Synchronous Transfer Mode) switching system. Also, unlike a conventional packet switching system that has a processor switch cells equivalent to packets through software processing, since an ATM switching system has hardware provided in a channel switch cells, it does not require complex protocols in switching cells, which realizes high speed communications at transfer rates up to several hundred megabits per second.
This makes it possible to flexibly provide services requiring different transmission speeds, and to efficiently utilize transmission paths.
In this operation, according to the VCI attached to a cell, a switching system processor designates to which buffer in a switching module of the ATM switching system the cell is to be written. The cells flow autonomously in the network according to this designation. Hence, this switching arrangement is called a self-routing (SR). The receiving subscriber extracts necessary cells flowing over ATM highways based on the VCIs attached to cells, and restores user information or payload data by eliminating headers from the cells.
FIG. 1 is a schematic view of a generic ATM exchanger used in ATM switching system.
In FIG. 1, trunks 102 accommodate respective subscriber lines 101 on the input side. A virtual channel controller (VCC) 105 receives outputs from the trunks 102.
Based on the call control information inputted from a processor (not shown) of the switching system, the VCC 105 exchanges the VCIs, which specify the cells' destinations, attached to the headers of the received cells from the respective input highways 104, with new VCIs specifying the next output node (ATM switching system). At the same time, the VCC 105 attaches to the head ends of the cells information specifying the path over which the cells are to be switched to be outputted to destined output highways 108 in a data format called tags.
A plurality of multiplexers (MUXs) 103 partially multiplex respective outputs from the VCC 105. Respective input highways 104 receive outputs from the corresponding multiplexers 103.
A multistage self-routing channel (MSSR) 106, which is a virtual channel, receives respective outputs from the MUXs 105. The MSSR 106 comprises a plurality of self-routing modules (SRMs) 107. The MSSR 106 has a plurality (ordinarily two (2) rows and three (3) stages) of SRMs 107. The configuration of the SRMs 107 are further elaborated later.
The MSSR 106 outputs cells to output highways 108, which are connected to respective demultiplexers (DMUXs) 109, which demultiplex the cells and output the demultiplexed cells to subscriber lines 111 through output trunks 110 corresponding respectively to the DMUXs 109.
FIG. 1 shows a configuration where cells flow in a single direction over the channels. It goes without saying that channels for cells flowing in the opposite directions can be configured similarly.
FIG. 2 shows an exemplary configuration of one of the SRMs 107 shown in FIG. 1.
In the example shown in FIG. 2, each of the SRMs 107 has two (2) input lines and two (2) output lines, and switches 201 are provided at the four (4) crossing points of the input lines and output lines. That is, the four (4) switches of an SRM 107 correspond with two (2) input lines and two (2) output lines. Although an actual channel may comprise more input lines and more output lines in reality since their basic connections are entirely similar to those in the example shown in FIG. 2, the SRMs 107 are explained by referring to the 2.times.2 exemplary configuration having two (2) input lines and two (2) output lines.
The switches 201 judge from the tag data attached to the head ends of cells inputted from input lines whether or not to switch the cells for acceptance. If the switches 201 judge whether or not to switch the cells by themselves, the switches 201 multiplex the cells on free time slots on output lines. Respective switches 201 independently perform the judging and switching operations through hardware processing.
As is evident from the above explanation, a fault in one of the switches 201 in any of the SRMs 107 shown in FIG. 1 causes severe trouble, such as a degradation in communications quality and a stoppage of communications all together through discarding ATM cells and incorrectly switching ATM cells. Hence, it is crucial to conduct a test for verifying the normality of the switches.
However, there is no known conventional system for efficiently testing the switches of an ATM exchanger. Especially in the configuration, shown in FIG. 1, of the MSSR 106 having the SRMs 107 connected in a plurality of stages, the more there are possible paths from an input line to an output line, the more there are the SRMs 107 in the MSSR 106. This causes an inevitable problem of how to efficiently test all such possible paths in realizing an ATM exchanger.